(1) Field of the Invention
This invention relates to fabrication methods used for semiconductor devices, and more specifically a process used to integrate logic and memory devices on a single semiconductor chip.
(2) Description of Prior Art
Advanced semiconductor chips, now being manufactured in industry, are composed of logic or memory devices. Logic devices are used to process information or data, while memory devices are used for data storage. These two types of devices can be found in almost all computers, however they are usually found on specific chips, reserved for either logic or memory applications. In systems in which logic and memory devices are packaged separately, data signals between the two may have to pass through several levels of packaging, which can result in undesirable propagation delays. In addition the manufacturing costs for fabricating wafers producing only logic chips, and wafers with only memory chips, are greater than if both logic and memory applications can be incorporated on the same chip. Therefore for performance and cost reasons the semiconductor industry has been motivated to produce a semiconductor chip with both the desired logic and memory requirements.
One difficulty encountered when attempting to integrate logic cells, with memory cells that are comprised of embedded dynamic random access memory, (DRAM), devices, is the ability to open contact holes, to regions of a semiconductor substrate, in thick insulator layers. The DRAM devices, comprised of bit line structures, as well as stacked capacitor structures, both located overlaying the semiconductor substrate, require thick insulator layers, to successfully isolate these components from adjacent conductive features. In addition with the use of sub--0.25 uM groundrules, the contact holes in the thick insulator layers can be designed to dimensions as narrow as 0.3 uM, in diameter, resulting in contact hole aspect ratios of about 7 to 1. This high contact hole aspect ratio is not only difficult to create, via anisotropic reactive ion etching procedures, but also difficult to fill, using conventional chemical vapor deposition, or plasma deposition procedures.
This invention will describe a process for integrating logic devices, and an embedded DRAM array, in which the aspect ratio for a contact hole, is reduced to about one half of the aspect ratio for a contact hole, used in conventional logic--DRAM integrations. This is accomplished using a two stage, contact hole opening, with the first stage forming a C1, first contact hole, in only the lower insulator layers, followed by a tungsten fill, which allows contact to underlying features in the logic and DRAM memory regions to be achieved. The second stage of this procedure features the creation of a C2, second contact hole, in upper insulator layers, directly overlying a tungsten filled, C1 contact holes After filling of the C2 contact holes with tungsten, a tungsten filled, narrow diameter, deep contact hole is established, achieved via a two stage procedure, which each procedure resulting in a contact hole with reduced aspect ratios. The first stage of this procedure, used to create tungsten filled, CI contact holes, also creates a dual shaped opening, allowing a damascene, tungsten bit line structure, to be realized, thus reducing bit line resistance, when compared to counterparts fabricated from metal silicide layers. Related prior art, such as Pittikoun et al, in U.S. Pat. No. 5,691,223, describe a process for forming a capacitor over a bit line structure, for DRAM applications, however tungsten silicide is used in place of tungsten, and more importantly a two stage contact hole opening, and fill, used in this invention to reduce the aspect ratio of the contact hole, is not described in this prior art.